High-speed programming of memory devices
US7900102B2 · kind B2 · utility
28Cited by
217References
41Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Dec 17, 2007 |
| Grant date | Mar 1, 2011 |
| Priority date | — |
| Expiry date | Mar 17, 2029 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2211/5621
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method for operating a memory that includes a plurality of analog memory cells includes storing data in a first group of the memory cells by writing respective first cell values to the memory cells in the first group. After storing the data, respective second cell values are read from the memory cells in the first group, and differences are found between the respective first and second cell values for each of one or more of the memory cells in the first group. The differences are processed to produce error information, and the error information is stored in a second group of the memory cells.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.