System and method for digital logic testing
US7900112B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jul 15, 2008 |
| Grant date | Mar 1, 2011 |
| Priority date | — |
| Expiry date | Apr 28, 2029 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F11/263
- WIPO fieldMeasurement
- WIPO sectorInstruments
Abstract
Some embodiments provide a method of digital logic design and digital logic testing of logic under test, the logic including latches, the latches including measure latches, which are latches that measure focal faults more than other latches, and care bit latches, which are latches that require specific input values to test a fault, wherein a focal fault is a randomly selected untested fault in the logic under test, the method comprising generating test patterns for the logic under test; fault simulating the test patterns on the logic under test; ranking measure latches based on the number of focal faults they respectively measure; and tracing back a number of levels from at least some of the highest ranked measure latches and inserting test observe latches. Other methods and systems are also provided.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.