Inventor · Waterbury, VT, US

Andrew Ferko

4Patents
2h-index
10Co-inventors
37Inventor score

Filing activity: Jan 23, 2001 → Aug 26, 2009

Most-cited inventions

PatentTitleAreaCited byStatus
US6782501B2 System for reducing test data volume in the testing of logic products Physics 17 Expired
US8209141B2 System and method for automatically generating test patterns for at-speed structural test of an integrated circuit device using an incremental approach to reduce test pattern count Physics 7 Active
US7103816B2 Method and system for reducing test data volume in the testing of logic products Physics 2 Expired
US7900112B2 System and method for digital logic testing Physics 2 Active

Source: USPTO / EPO open patent data. Inventor disambiguation is heuristic; counts are objective bibliographic measures.