Methods and devices for a high-k stacked capacitor
US7902033B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Feb 12, 2008 |
| Grant date | Mar 8, 2011 |
| Priority date | — |
| Expiry date | Sep 23, 2028 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D1/716
Abstract
An embodiment generally relates a method of forming capacitors. The method includes forming a plurality of holes within a protective overcoat or backend dielectric layer of an integrated circuit and depositing multiple layers of metal, each layer of metal electrically tied to an associated electrode. The method also includes alternately depositing multiple layers of dielectric between the multiple layers of metal and coupling a bottom layer of the multiple layers of metal to a contact node in a top metal layer of the integrated circuit.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.