Method for forming active and gate runner trenches
US7902071B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Jul 6, 2010 |
| Grant date | Mar 8, 2011 |
| Priority date | — |
| Expiry date | Jul 6, 2030 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY10S438/95
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method for forming a trench-gated field effect transistor (FET) includes the following steps. Using a first mask, defining and simultaneously forming a plurality of active gate trenches and at least one gate runner trench extending to a first depth within a silicon region such that (i) the at least one gate runner trench has a width greater than a width of each of the plurality of active gate trenches, and (ii) the plurality of active gate trenches are contiguous with the at least one gate runner trench; and using the first mask and a second mask for protecting the at least one gate runner trench, further extending only the plurality of active gate trenches to a second and final depth within the silicon region.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.