Multichip package leadframe including electrical bussing
US7902655B1 · kind B1 · utility
0Cited by
4References
31Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Apr 3, 2007 |
| Grant date | Mar 8, 2011 |
| Priority date | — |
| Expiry date | Feb 24, 2029 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/30107
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Embodiments of the present invention provide electrical bussing for multichip leadframes. In various embodiments, a leadframe may comprise a first die paddle for receiving a first microelectronic device, a second die paddle for receiving a second microelectronic device, and at least one electrical bus disposed between the first die paddle and the second die paddle. In various ones of these embodiments, the electrical bus may be configured to supply a potential to at least one of the first and second microelectronic devices.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.