Composite layered chip package and method of manufacturing same
US7902677B1 · kind B1 · utility
Assignees
Inventors
Key dates
| Filing date | Oct 28, 2009 |
| Grant date | Mar 8, 2011 |
| Priority date | — |
| Expiry date | Nov 5, 2029 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/3025
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A composite layered chip package includes a plurality of subpackages stacked. Each subpackage includes a main body, and wiring disposed on a side surface of the main body. The main body has a main part that includes at least one first-type layer portion. For any two vertically adjacent subpackages, the main body of the lower subpackage has a plurality of first terminals that are arranged on the top surface of the main part, while the main body of the upper subpackage has a plurality of second terminals that are arranged on the bottom surface of the main part. The main part of the main body of at least one of the plurality of subpackages includes at least one second-type layer portion. The first-type layer portion includes a conforming semiconductor chip, while the second-type layer portion includes a defective semiconductor chip.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.