Structure and manufacturing method of a chip scale package with low fabrication cost, fine pitch and high reliability solder bump
US7902679B2 · kind B2 · utility
81Cited by
141References
20Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Oct 31, 2007 |
| Grant date | Mar 8, 2011 |
| Priority date | — |
| Expiry date | Oct 31, 2027 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/351
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A new method and package is provided for the mounting of semiconductor devices that have been provided with small-pitch Input/Output interconnect bumps. Fine pitch solder bumps, consisting of pillar metal and a solder bump, are applied directly to the I/O pads of the semiconductor device, the device is then flip-chip bonded to a substrate. Dummy bumps may be provided for cases where the I/O pads of the device are arranged such that additional mechanical support for the device is required.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.