Patent · US Active

Semiconductor arrangement and method for producing a semiconductor arrangement

US7902683B2 · kind B2 · utility

0Cited by

4References

23Claims

0Family size

Assignee

Infineon Technologies AG · DE

Inventors

Frank Pueschner · Kelheim, DE
Erik Heinemann · Regensburg, DE
Stephan Janka · Regensburg, DE

Key dates

Filing date	Mar 23, 2006
Grant date	Mar 8, 2011
Priority date	—
Expiry date	May 8, 2028

Classification

Technology area (CPC H)Electricity
CPC primaryH01L2924/3511
WIPO fieldSemiconductors
WIPO sectorElectrical engineering

Abstract

A semiconductor arrangement having at least one semiconductor chip, which has, on one surface, an integrated circuit and at least one contact element which is electrically conductively connected to the latter, and having an edge protector, which at least partially covers an edge region on the surface of the semiconductor, the edge region extending along outer edges of the semiconductor chip. A method for manufacturing the above-mentioned semiconductor arrangement.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.