Multiple reference phase locked loop
US7902886B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Oct 28, 2008 |
| Grant date | Mar 8, 2011 |
| Priority date | — |
| Expiry date | Oct 28, 2028 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03L7/183
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A multi reference phase locked loop (MPLL) generates a high speed clock frequency and phase locks it to a lowest common reference frequency derived from a selected one of at least two reference clocks. One of the reference clocks is a system reference clock in a FBDIMM system, another may be a forwarded clock in an AMB2. A prescaler reduces the frequency of at least the forwarded clock to the lowest common reference frequency which is the frequency of the system reference clock. A PLL at the core of the MPLL may be locked to the forwarded clock or the system reference clock for generating a high speed clock. A feedback divider generates the feedback clock for the PLL as well as other clocks required in the system. Furthermore, the MPLL provides a number of clocking modes, including modes to facilitate testing and powering down of sections of the circuitry for conserving power.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.