Patent · US Active

Testing circuit split between tiers of through silicon stacking chips

US7904770B2 · kind B2 · utility

5Cited by

5References

24Claims

0Family size

Assignee

QUALCOMM Incorporated · US

Inventor

Thomas R. Toms · Dripping Springs, US

Key dates

Filing date	Sep 9, 2008
Grant date	Mar 8, 2011
Priority date	—
Expiry date	May 6, 2029

Classification

Technology area (CPC H)Electricity
CPC primaryH01L2924/0002
WIPO fieldMeasurement
WIPO sectorInstruments

Abstract

A method of testing a die having a non-testable circuit, where the non-testable circuit is logically incomplete and forms part of a logically complete multiple tier circuit. The method includes reconfiguring a tier-to-tier input point or tier-to-tier output point associated with a primary path of the non-testable circuit to create a logically complete secondary path for the tier-to-tier point such that the non-testable circuit can be tested. Testable dies and methods of preparing such dies are also provided.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.