Reduced-edge radiation-tolerant non-volatile transistor memory cells

US7906805B2 · kind B2 · utility

Assignee

• Actel Corporation · US

Inventors

• Michael A. Sadd · Austin, US
• Fethi Dhaoui · Tracy, US
• John McCollum · Saratoga, US
• Richard Chan · Village of La Jolla, US

Key dates

• Filing date: Aug 22, 2008
• Grant date: Mar 15, 2011
• Expiry date: Sep 3, 2028

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D30/0413

Abstract

An edgeless one-transistor flash memory array includes transistors that have two polysilicon gate layers that overlay an active region. The bottom polysilicon gate layer is electrically isolated. The memory is configured such that current passes from drain to source under the bottom polysilicon layer, such that it does not approach a field oxide region. An edgeless two-transistor programmable memory includes memory cells that have two active devices. Two polysilicon gate layers overlay two active regions and are shared between the two active devices. One of the devices is used to program and erase the cell while the other used as a programmable switch in a programmable logic device. The bottom polysilicon gate layer is electrically isolated. The memory is configured such that current passes from drain to source under the bottom polysilicon layer, such that it does not approach a field oxide region.