Semiconductor device having reduced thermal interface material (TIM) degradation and method therefor
US7906845B1 · kind B1 · utility
14Cited by
16References
20Claims
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Key dates
| Filing date | Apr 23, 2008 |
| Grant date | Mar 15, 2011 |
| Priority date | — |
| Expiry date | Oct 1, 2028 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/16251
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A semiconductor device has a substrate having a top and bottom surface and a plurality of metal layers. A first die is electrically coupled to the top surface of the substrate. A lid member is attached to a top surface of the die and to the top surface of the substrate. A layering is formed on portions of a top surface of the lid member. The layering will have a different coefficient of thermal expansion (CTE) than the lid member.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.