Carry-select adder structure and method to generate orthogonal signal levels
US7908308B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | May 15, 2007 |
| Grant date | Mar 15, 2011 |
| Priority date | — |
| Expiry date | Nov 29, 2029 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F7/507
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A Carry-Select Adder structure comprising a carry generation network and a multiplexer to select a particular pre-calculatad sum of a bit-group via orthogonal signal levels of a Hot-Carry signal provided by said carry generation network (21), wherein in order to provide orthogonal signal levels of said Hot-Carry signal, the carry generation network (21) comprises two carry lookahead trees (22, 23) working in parallel to each other, wherein a first carry lookahead tree (22) provides a first signal level of the Hot-Carry signal, and a second carry lookahead tree (23) provides a second, compared to the first signal level inverse signal level of the Hot-Carry signal. Furthermore a method to operate such a Carry-Select Adder is described.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.