Reducing gate CD bias in CMOS processing

US7910422B2 · kind B2 · utility

Assignee

• TEXAS INSTRUMENTS INCORPORATED · US

Inventors

• Freidoon Mehrad · Plano, US
• Jinhan Choi · San Ramon, US
• Frank Scott Johnson · South San Francisco, US

Key dates

• Filing date: Sep 30, 2008
• Grant date: Mar 22, 2011
• Expiry date: Apr 25, 2029

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D84/0179

Abstract

A method of forming an integrated circuit having an NMOS transistor and a PMOS transistor is disclosed. The method includes performing pre-gate processing in a NMOS region and a PMOS region over and/or in a semiconductor body, and depositing a polysilicon layer over the semiconductor body in both the NMOS and PMOS regions. The method further includes performing a first type implant into the polysilicon layer in one of the NMOS region and PMOS region, and performing an amorphizing implant into the polysilicon layer in both the NMOS and PMOS regions, thereby converting the polysilicon layer into an amorphous silicon layer. The method further includes patterning the amorphous silicon layer to form gate electrodes, wherein a gate electrode resides in both the NMOS and PMOS regions.