High voltage ESD LDMOS-SCR with gate reference voltage

US7910950B1 · kind B1 · utility

Assignee

• NATIONAL SEMICONDUCTOR CORPORATION · US

Inventors

• Vladislav Vashchenko · Palo Alto, US
• Peter J. Hopper · San Jose, US

Key dates

• Filing date: Apr 13, 2006
• Grant date: Mar 22, 2011
• Expiry date: Jan 10, 2029

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D62/109

Abstract

In an LDMOS-SCR ESD protection structure gate voltage of an ESD protection LDSCR is defined by connecting the gate to the source of a reference LDSCR. The reference LDSCR is implemented as a self-triggering device in which the snapback drain-source voltage (avalanche breakdown voltage) is controlled to be lower than that for the major LDSCR by adjusting the RESURF layer-composite overlap for the reference LDSCR to be different to that of the major LDSCR.