Semiconductor device with interface circuit and method of configuring semiconductor devices
US7910956B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Dec 18, 2009 |
| Grant date | Mar 22, 2011 |
| Priority date | — |
| Expiry date | Dec 18, 2029 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY02P80/30
Abstract
Methods and devices yielding an improved semiconductor device with interface circuit are disclosed. Configuring a semiconductor with parallel device features reduces process variation (e.g., lithographically-induced process variation or other defects). Embodiments of the present invention provide semiconductor devices with I/O cell device features (e.g., I/O gates or core gates) laid out in parallel. Additionally, embodiments of the present invention can allow patterning devices to be made to more exacting tolerances because some patterning devices may have a higher capability along one axis than another. Embodiments of the present invention also include a semiconductor device having like-functioned I/O cells arranged such that their layouts and rotational orientations with respect to their corresponding core remain constant. Furthermore, disclosed semiconductor devices may include at least one circuit cell having non-parallel features, where the circuit cell is arranged either within the core or within a corresponding interface circuit cell.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.