Methods for forming self-aligned dual stress liners for CMOS semiconductor devices
US7911001B2 · kind B2 · utility
23Cited by
1References
13Claims
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Key dates
| Filing date | Jul 15, 2007 |
| Grant date | Mar 22, 2011 |
| Priority date | — |
| Expiry date | Mar 3, 2028 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D84/0186
Abstract
CMOS (complementary metal oxide semiconductor) fabrication techniques are provided to form DSL (dual stress liner) semiconductor devices having non-overlapping, self-aligned, dual stress liner structures.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.