Programming PAD ESD protection circuit
US7911752B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Oct 29, 2009 |
| Grant date | Mar 22, 2011 |
| Priority date | — |
| Expiry date | Nov 25, 2029 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH02H9/046
- WIPO fieldElectrical machinery, apparatus, energy
- WIPO sectorElectrical engineering
Abstract
An electrostatic discharge (ESD) protection circuit is electrically connected to a core circuit for preventing ESD charges from reaching the core circuit. The ESD protection circuit includes a pad, a pass transistor, a transistor, a capacitor, a resistor, and a delay trigger unit. The pass transistor controls passage of charges from the pad to the core circuit. The transistor sinks ESD charges during an ESD zapping event. The capacitor and the resistor couple voltage at the pad to a control electrode of the transistor for turning on the transistor during the ESD zapping event. The delay trigger unit retards transmission of low voltage to a control electrode of the pass transistor for keeping the pass transistor turned off during the ESD zapping event.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.