Mapping the threads of a CTA to the elements of a tile for efficient matrix multiplication
US7912889B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 16, 2006 |
| Grant date | Mar 22, 2011 |
| Priority date | — |
| Expiry date | Jan 20, 2030 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F17/16
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
The present invention enables efficient matrix multiplication operations on parallel processing devices. One embodiment is a method for mapping CTAs to result matrix tiles for matrix multiplication operations. Another embodiment is a second method for mapping CTAs to result tiles. Yet other embodiments are methods for mapping the individual threads of a CTA to the elements of a tile for result tile computations, source tile copy operations, and source tile copy and transpose operations. The present invention advantageously enables result matrix elements to be computed on a tile-by-tile basis using multiple CTAs executing concurrently on different streaming multiprocessors, enables source tiles to be copied to local memory to reduce the number accesses from the global memory when computing a result tile, and enables coalesced read operations from the global memory as well as write operations to the local memory without bank conflicts.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.