Norbert Juffa
33Patents
19h-index
15Co-inventors
74Inventor score
Filing activity: Oct 10, 1997 → Mar 23, 2011
Most-cited inventions
| Patent | Title | Area | Cited by | Status |
|---|---|---|---|---|
| US6105129A | Converting register data from a first format type to a second format type if a second type instruction consumes data produced by a first type instruction | Physics | 238 | Expired |
| US7912889B1 | Mapping the threads of a CTA to the elements of a tile for efficient matrix multiplication | Physics | 105 | Active |
| US7792895B1 | Efficient matrix multiplication on a parallel processing device | Physics | 102 | Active |
| US6134574A | Method and apparatus for achieving higher frequencies of exactly rounded results | Physics | 66 | Expired |
| US6223198A | Method and apparatus for multi-function arithmetic | Physics | 57 | Expired |
| US6397239B2 | Floating point addition pipeline including extreme value, comparison and accumulate functions | Electricity | 41 | Expired |
| US8327123B2 | Maximized memory throughput on parallel processing devices | Physics | 34 | Active |
| US6393555B1 | Rapid execution of FCMOV following FCOMI by storing comparison result in temporary register in floating point unit | Physics | 34 | Expired |
| US6397238B2 | Method and apparatus for rounding in a multiplier | Physics | 31 | Expired |
| US8860741B1 | Graphics processor with memory management unit and cache coherent link | Physics | 30 | Active |
| US6256653A | Multi-function bipartite look-up table | Physics | 28 | Expired |
| US7506134B1 | Hardware resource based mapping of cooperative thread arrays (CTA) to result matrix tiles for efficient matrix multiplication in computing system comprising plurality of multiprocessors | Physics | 28 | Active |
| US7925860B1 | Maximized memory throughput using cooperative thread arrays | Physics | 27 | Active |
| US6223192A | Bipartite look-up table with output values having minimized absolute error | Physics | 26 | Expired |
| US6405305B1 | Rapid execution of floating point load control word instructions | Physics | 23 | Expired |
| US6115732A | Method and apparatus for compressing intermediate products | Physics | 22 | Expired |
| US6408379B1 | Apparatus and method for executing floating-point store instructions in a microprocessor | Physics | 21 | Expired |
| US6115733A | Method and apparatus for calculating reciprocals and reciprocal square roots | Physics | 20 | Expired |
| US6425074B1 | Method and apparatus for rapid execution of FCOM and FSTSW | Physics | 19 | Expired |
| US6374345B1 | Apparatus and method for handling tiny numbers using a super sticky bit in a microprocessor | Physics | 13 | Expired |
| US6247117A | Apparatus and method for using checking instructions in a floating-point execution unit | Physics | 13 | Expired |
| US5918062A | Microprocessor including an efficient implemention of an accumulate instruction | Electricity | 12 | Expired |
| US6370637B1 | Optimized allocation of multi-pipeline executable and specific pipeline executable instructions to execution pipelines based on criteria | Physics | 8 | Expired |
| US6442677B1 | Apparatus and method for superforwarding load operands in a microprocessor | Physics | 8 | Expired |
| US6298367A | Floating point addition pipeline including extreme value, comparison and accumulate functions | Electricity | 7 | Expired |
Source: USPTO / EPO open patent data. Inventor disambiguation is heuristic; counts are objective bibliographic measures.