Duty cycle correction apparatus and semiconductor integrated circuit having the same
US7915939B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 19, 2009 |
| Grant date | Mar 29, 2011 |
| Priority date | — |
| Expiry date | Mar 19, 2029 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K2005/00052
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A duty cycle correction apparatus includes a fixed delay unit configured to set a fixed delay time to a DLL clock signal and generate a delay rising clock signal; a variable delay unit configured to delay the DLL clock signal in response to a control signal and generate a delay falling clock signal; a duty cycle correction unit configured to generate a correction rising clock signal and a correction falling clock signal that are toggled in conformity with edge timing of the delay rising clock signal and the delay falling clock signal; and a delay control unit configured to detect duty cycles of the correction rising clock signal and the correction falling clock signal and generate the control signal.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.