SCR matrix storage device
US7916530B2 · kind B2 · utility
5Cited by
29References
28Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Dec 8, 2009 |
| Grant date | Mar 29, 2011 |
| Priority date | — |
| Expiry date | Dec 8, 2029 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY10T29/49002
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
In various embodiments, an addressable storage matrix includes a first plurality of intersection points, at least some of which are bridged by two-terminal non-linear elements that exhibit a threshold below which current flow is significantly lower than if the threshold is exceeded, as well as, disposed at each intersection point bridged by a non-linear element, a programmable material in series with the non-linear element and determining a bit state for the corresponding intersection point.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.