Systems and methods for testing and diagnosing delay faults and for parametric testing in digital circuits
US7917319B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Feb 6, 2008 |
| Grant date | Mar 29, 2011 |
| Priority date | — |
| Expiry date | Mar 16, 2029 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG01R31/31858
- WIPO fieldMeasurement
- WIPO sectorInstruments
Abstract
Delay-fault testing and parametric analysis systems and methods utilizing one or more variable delay time-base generators. In embodiments of the delay-fault testing systems, short-delay logic paths are provided with additional scan-chain memory elements and logic that, in conjunction with the one or more variable-delay time-base generators, provides the effect of over-clocking without the need to over-clock. Related methods provide such effective over-clocking. In embodiments of parametric analysis systems, test point sampling elements and analysis circuitry are clocked as a function of the output of the one or more variable-delay time-base generators to provide various parametric analysis functionality. Related methods address this functionality.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.