Method and cache control circuit for replacing cache lines using alternate PLRU algorithm and victim cache coherency state
US7917700B2 · kind B2 · utility
1Cited by
9References
16Claims
0Family size
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Key dates
| Filing date | Oct 25, 2007 |
| Grant date | Mar 29, 2011 |
| Priority date | — |
| Expiry date | Jul 30, 2029 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F12/128
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method and a cache control circuit for replacing a cache line using an alternate pseudo least-recently-used (PLRU) algorithm with a victim cache coherency state, and a design structure on which the subject cache control circuit resides are provided. When a requirement for replacement in a congruence class is identified, a first PLRU cache line for replacement and an alternate PLRU cache line for replacement in the congruence class are calculated. When the first PLRU cache line for replacement is in the victim cache coherency state, the alternate PLRU cache line is picked for use.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.