SDRAM controller
US7917706B1 · kind B1 · utility
Assignee
Inventor
Key dates
| Filing date | Dec 15, 2003 |
| Grant date | Mar 29, 2011 |
| Priority date | — |
| Expiry date | Jun 13, 2024 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F13/1642
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A SDRAM controller prioritizes memory access requests to maximize efficient use of the bandwidth of the memory data bus, and also gives different priorities to access requests received on its different inputs. The SDRAM controller has multiple inputs, at least one of which allows connections to multiple bus master devices. The SDRAM controller forms a queue of bus access requests, based amongst other things on a relative priority given to the input on which a request is received. When a request is received on an input which allows connections to multiple bus master devices, the SDRAM controller forms the queue of bus access requests, based amongst other things on a relative priority given to the bus master device which made the request.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.