Instruction code compression using instruction codes with reuse flags
US7917733B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Jun 26, 2008 |
| Grant date | Mar 29, 2011 |
| Priority date | — |
| Expiry date | Sep 24, 2029 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F9/3802
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An instruction code compression method and an instruction fetch circuit which are capable of reducing both the number of fetches and program codes. A reuse flag is provided in an upper bit group including operational codes, and a lower bit group including operands and having the same number of bits as the upper bit group. When 2N+1 (N is an integer of 1 or more) instruction codes having the same upper bit group continues in a series of instruction codes, respective reuse flags of the lower bit group of a 2n-th (n is an integer of 1 or more and N or less) instruction code and a (2n+1)-th instruction code in the series of instruction codes are set to “1”, and the lower bit groups of the 2n-th and (2n+1)-th instruction codes are integreted into one compressed instruction code.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.