Patent · US Active

System and method for circuit schematic generation

US7917877B2 · kind B2 · utility

183Cited by

2References

24Claims

0Family size

Assignee

Cadence Design Systems, Inc. · US

Inventors

Balvinder Singh · Faridabad, IN
Donald J. O'Riordan · Sunnyvale, US
Bogdan G. Arsintescu · San Jose, US
Alka Goel · Barwala, IN
Devendra Deshpande · Noida, IN

Key dates

Filing date	May 9, 2008
Grant date	Mar 29, 2011
Priority date	—
Expiry date	Jun 10, 2029

Classification

Technology area (CPC G)Physics
CPC primaryG06F2111/12
WIPO fieldComputer technology
WIPO sectorElectrical engineering

Abstract

The present invention provides a system and method for generating circuit schematic that includes extracting connectivity data of a plurality of devices from a netlist, categorizing the plurality of devices into groups, placing Schematic Analog Placement Constraints on all the instances by identifying instances among the groups that match with a circuit template (in-built as well as user-specified), creating a BFS instance tree of tree instances, creating a two terminal device clusters and creating instance attachments. Using the constraints during grid based placement and eventually generated schematic which look like analog schematic.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.