Method of anti-stiction dimple formation under MEMS
US7919006B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Oct 31, 2007 |
| Grant date | Apr 5, 2011 |
| Priority date | — |
| Expiry date | Oct 25, 2029 |
Classification
- Technology area (CPC B)Performing Operations; Transporting
- CPC primaryB81B3/001
- WIPO fieldMicro-structural and nano-technology
- WIPO sectorChemistry
Abstract
A method for making a MEMS structure comprises patterning recesses in a dielectric layer overlying a substrate, each recess being disposed between adjacent mesas of dielectric material. A conformal layer of semiconductor material is formed overlying the recesses and mesas. The conformal layer is chemical mechanically polished to form a chemical mechanical polished surface, wherein the chemical mechanical polishing is sufficient to create dished portions of semiconductor material within the plurality of recesses. Each dished portion has a depth proximate a central portion thereof that is less than a thickness of the semiconductor material proximate an outer portion thereof. A semiconductor wafer is then bonded to the chemical mechanical polished surface. The bonded semiconductor wafer is patterned with openings according to the requirements of a desired MEMS transducer. Lastly, the MEMS transducer is released. Releasing advantageously exposes anti-stiction features formed from outer edges of the dished portion of semiconductor material.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.