Multiple output level shifter
US7919983B1 · kind B1 · utility
Assignee
Inventor
Key dates
| Filing date | Dec 21, 2009 |
| Grant date | Apr 5, 2011 |
| Priority date | — |
| Expiry date | Dec 21, 2029 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K19/018528
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A level shifter for integrated circuits includes input stage transistors, reference stage transistors, a cascode stage coupled to the input stage and the reference stage transistors and a pair of comparators. The cascode stage generates a first cascode output and a second cascode output. The input stage transistors selectively conduct a low reference voltage as the first cascode output based on a pair of inputs provided to the input stage transistors. The reference stage transistors selectively conduct a high reference voltage as the second cascode output based on a first comparator output and a second comparator output. The pair of comparators generate the first and the second comparator outputs based on the first and the second cascode outputs.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.