Patent · US Active

Integrated circuits and methods for operating the same using a plurality of buffer circuits in an access operation

US7920430B2 · kind B2 · utility

0Cited by

12References

11Claims

0Family size

Assignee

Qimonda AG · DE

Inventors

Gert Koebernik · Unterhaching, DE
Jan Gutsche · Munich, DE
Christoph Friederich · Birkenfeld, DE
Detlev Richter · Unterhaching, DE

Key dates

Filing date	Jul 1, 2008
Grant date	Apr 5, 2011
Priority date	—
Expiry date	Jan 9, 2029

Classification

Technology area (CPC G)Physics
CPC primaryG11C2211/5642
WIPO fieldComputer technology
WIPO sectorElectrical engineering

Abstract

In an embodiment, an integrated circuit having a memory cell arrangement is provided. The memory cell arrangement may include a plurality of multiple bit information storing memory cells, a plurality of buffer circuits, each buffer circuit being coupled to at least one multiple bit information storing memory cell of the plurality of multiple bit information storing memory cells, and a controller configured to control an access operation to access at least one multiple bit information storing memory cell using the buffer circuit coupled to the at least one multiple bit information storing memory cell to be accessed, and a buffer circuit of at least one other multiple bit information storing memory cell being coupled to at least one other multiple bit information storing memory cell.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.