Address control circuit of semiconductor memory apparatus
US7920437B2 · kind B2 · utility
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7References
25Claims
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Key dates
| Filing date | Jun 30, 2009 |
| Grant date | Apr 5, 2011 |
| Priority date | — |
| Expiry date | Sep 23, 2029 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C11/406
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An address control circuit for a semiconductor memory apparatus so as to make a refresh operation test possible by designating a refresh address is presented. The circuit includes a buffer block, a decoder, and a latch block. The buffer block receives coding information coded testing address information in accordance to a test signal. The decoder generates a test refresh address by decoding the coding information. The latch block latches the test refresh address depending on the test signal.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.