Adjustble gain signal processing device
US7924190B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 18, 2009 |
| Grant date | Apr 12, 2011 |
| Priority date | — |
| Expiry date | Sep 18, 2029 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03M1/504
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A CLK generating section of a digital ALC generates a multiplication clock signal that is obtained by multiplying a triangular wave generated at a triangular wave generating circuit. On the basis of the multiplication clock signal, a signal converting section converts a one-bit digital audio signal outputted from an outputting stage into a multi-bit digital signal, and monitors a voltage value of an input signal. A level controlling section controls a voltage level on the basis of a target level inputted from an exterior of an LSI. On the basis of a control signal inputted from an exterior of the LSI, a volume controlling section outputs, to a PGA, a gain adjusting signal so as to vary a waveform of an input signal.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.