Methods for identifying array areas in dies formed on a wafer and methods for setting up such methods
US7925072B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 8, 2007 |
| Grant date | Apr 12, 2011 |
| Priority date | — |
| Expiry date | Feb 9, 2030 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06T2207/30148
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Methods for identifying array areas in dies formed on a wafer and methods for setting up such methods are provided. One method for identifying array areas in dies formed on a wafer includes comparing an array pattern in a template image acquired in one of the array areas to a search area image acquired for the wafer. The method also includes determining areas in the search area image in which a pattern is formed that substantially matches the array pattern in the template image based on results of the comparing step. In addition, the method includes identifying the array areas in the dies formed on the wafer based on results of the determining step.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.