Method and apparatus for controlling memory array gating when a processor executes a low confidence branch instruction in an information handling system
US7925853B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jan 4, 2008 |
| Grant date | Apr 12, 2011 |
| Priority date | — |
| Expiry date | Nov 19, 2029 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY02D10/00
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An information handling system includes a processor with an array power management controller. The array power management controller gates off a memory array, such as a cache, to conserve power whenever a group of instructions in a branch instruction queue together as a group exhibits a confidence in the accuracy of branch predictions of branch instructions therein that is less than a first predetermined threshold confidence threshold. In one embodiment of the information handling system, the array power management controller speculatively inhibits the gating off of the memory array when confidence in the accuracy of a branch prediction for a particular currently issued branch instruction exhibits less than a second predetermined threshold confidence threshold. In this manner, the array power management controller again allows access to the memory array in the event a branch redirect is likely.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.