Method for increasing cache directory associativity classes via efficient tag bit reclaimation
US7925857B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jan 24, 2008 |
| Grant date | Apr 12, 2011 |
| Priority date | — |
| Expiry date | Jul 12, 2029 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F12/0817
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
In a method of generating a cache directory to include a plurality of associativity classes, each associativity class includes an address tag including a plurality of address bits. Each address tag is configured to store a unique address to a specific location in an memory space. An amount of memory that is in an actually configured portion of the memory space is determined. A minimum number of bits necessary to address each memory location in the actually configured portion of the memory space is determined. Each address tag is configured in each associativity class to include the minimum number of bits necessary to address each memory location in the actually configured portion of the memory space. The cache directory is configured to include a maximum number of associativity classes per line in the cache directory.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.