Memory device with non-uniform programming levels
US7925936B1 · kind B1 · utility
Assignee
Inventor
Key dates
| Filing date | Jul 11, 2008 |
| Grant date | Apr 12, 2011 |
| Priority date | — |
| Expiry date | May 23, 2029 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F11/1048
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method for storing data in a memory, which includes a plurality of analog memory cells, includes defining programming levels that represent respective combinations of at least first and second bits and are represented by respective nominal storage values. The data is stored by mapping the data to storage values selected from among the nominal storage values and writing the storage values to the memory cells. A condition is defined over two or more bit-specific error rates applicable respectively to at least the first and second bits. The bit-specific error rates include a first bit-specific error rate computed over the data stored by the first bits and a second bit-specific error rate computed, separately from the first bit-specific error rate, over the data stored by the second bits. The nominal storage values are set based on the bit-specific error rates so as to meet the condition.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.