Apparatus for testing embedded memory read paths

US7925937B2 · kind B2 · utility

Assignee

• Advanced Micro Devices, Inc. · US

Inventors

• Joel Thornton Irby · Austin, US
• Grady L. Giles · Austin, US
• Alexander W. Schaefer · Austin, US
• Gregory A. Constant · Austin, US
• Floyd L. Dankert · Austin, US
• Amy M. Novak · Austin, US

Key dates

• Filing date: Jan 7, 2008
• Grant date: Apr 12, 2011
• Expiry date: Aug 13, 2029

Classification

• Technology area (CPC G): Physics
• CPC primary: G11C2029/3202
• WIPO field: Computer technology
• WIPO sector: Electrical engineering

Abstract

An integrated circuit. The integrated circuit includes a plurality of logic circuits. The integrated circuit further includes a scan chain including a plurality of scan elements coupled in series, wherein the scan chain is configured to load stimulus data to be applied to the logic circuits for testing. The scan chain is further configured to capture data subsequent to applying the stimulus data. The integrated circuit also includes an embedded memory having a read port, wherein the read port is coupled to one or more of the plurality of logic circuits via a read path. The embedded memory includes a virtual entry having a plurality of scan-controllable storage elements. During testing, the virtual entry is operable to apply transition data to the read path in order to cause logic state transitions in the one or more logic circuits in the read path.