Design-For-testability planner
US7926012B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 6, 2007 |
| Grant date | Apr 12, 2011 |
| Priority date | — |
| Expiry date | Dec 15, 2028 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F30/333
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method is provided to improve the usability of Design-For-Testability Synthesis (DFTS) tools and to increase the design process productivity. The method comprises receiving a list of testability and design impact analysis functions, to be performed on the circuit, also referred to as a device under test (DUT). The impact analysis leads to the creation of logical transformations, which can be selected by a user with one or more available transformation methods from a list including, but not limited to, boundary scan test logic insertion, scan test logic insertion, memory BIST (built-in-self-test) logic insertion, and logic BIST logic insertion, and scan test data compression insertion logic insertion.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.