Simplified double mask patterning system
US7927782B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Dec 28, 2007 |
| Grant date | Apr 19, 2011 |
| Priority date | — |
| Expiry date | Jan 22, 2029 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY10T428/24802
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
One embodiment of the present invention relates to a method for which a two mask lithography process can be used to reduce design density. The two mask process uses a first mask to expose a first photoresist layer located above a hard mask layer. The first photoresist is exposed in such a way that the level forms one or more lines, on opposite sides of a cell boundary. The hard mask is then etched. A second photoresist layer is deposited above the hard mask. The second mask is used to expose the second photoresist layer in such a way that a space is formed along the cell boundary equal to the minimum space of the level as required by the design rules. The hard mask is then etched again. The hard mask is subsequently used to pattern the layer below it. Other methods and structures are also disclosed.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.