Method for forming a transistor having gate dielectric protection and structure
US7927989B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jul 27, 2007 |
| Grant date | Apr 19, 2011 |
| Priority date | — |
| Expiry date | Feb 23, 2029 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D62/822
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A transistor structure is formed by providing a semiconductor substrate and providing a gate above the semiconductor substrate. The gate is separated from the semiconductor substrate by a gate insulating layer. A source and a drain are provided adjacent the gate to define a transistor channel underlying the gate and separated from the gate by the gate insulating layer. A barrier layer is formed by applying nitrogen or carbon on opposing outer vertical sides of the transistor channel between the transistor channel and each of the source and the drain. In each of the nitrogen and the carbon embodiments, the vertical channel barrier retards diffusion of the source/drain dopant species into the transistor channel. There are methods for forming the transistor structure.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.