Structure for a semiconductor device and a method of manufacturing the same
US7928006B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Sep 8, 2006 |
| Grant date | Apr 19, 2011 |
| Priority date | — |
| Expiry date | Feb 27, 2028 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/76807
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
There is described a method of manufacturing a damascene interconnect (1) for a semiconductor device. A non conductive diffusion barrier (10) is formed over the wall(s) of a passage (7) defined by a porous low K di-electric material (6) and over the surface of a copper region (3) that closes one end of the passage (7). The non-conductive barrier layer (10) is plasma treated to transform an upper portion thereof (10b) into a conductive layer, while a low portion thereof (10a) comprising material that has penetrated pores of the di-electric material remains non-conductive. The passage (7) is then filled with a second copper region (13) forming an electrical interconnect with the first copper region (3) via the now conductive upper portion (1Ob) of the barrier (10). As a person skilled in the art will know, all embodiments of the invention described and claimed in this document may be combined without departing from the scope of the invention.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.