Integrated circuit with a power transistor gate bias controlled by the leakage current
US7928797B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Oct 29, 2009 |
| Grant date | Apr 19, 2011 |
| Priority date | — |
| Expiry date | Oct 29, 2029 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K19/00384
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
The invention relates to electronic integrated circuits capable of operating either in active mode or in standby mode and of having, in standby mode, a very low current consumption. According to the invention, the leakage current of a power transistor inserted in series between a supply terminal and an active circuit is controlled by a gate reverse overbias in the following manner: a voltage step-up charge pump generates a gate bias voltage from pulses delivered by an oscillator having its frequency controlled by a current. The control current Ic is the leakage current of a transistor having technological characteristics similar to those of the power transistor. The system optimizes the current consumption in standby mode, the frequency of the oscillator being reduced when the gate is biased so as to minimize the leakage current. The invention is applicable to circuits powered by a battery or a cell (mobile telephones, cameras, portable computers, etc.).
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.