Embedded DRAM with bias-independent capacitance
US7929359B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Nov 13, 2008 |
| Grant date | Apr 19, 2011 |
| Priority date | — |
| Expiry date | Mar 28, 2029 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10B12/50
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An embedded memory system that includes DRAM cells and logic transistors. The capacitor of the embedded memory responds to a positive bias voltage of ½ Vdd. The wordline driver of a p-channel access transistor applying the positive power supply voltage when the p-channel access FET is not being accessed and a voltage lower than the threshold voltage of the p-channel access FET is being accessed. For DRAM cells containing an n-channel access FET, the wordline driver applies either a negative voltage or the ground voltage to the n-channel access FET when the DRAM cell is not being accessed. A second voltage composed of Vdd and a boosted voltage is applied to the n-channel FET when the DRAM cell is being accessed.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.