Patent · US Active

Circuit using a shared delay locked loop (DLL) and method therefor

US7929361B2 · kind B2 · utility

4Cited by

14References

20Claims

0Family size

Assignee

Advanced Micro Devices, Inc. · US

Inventors

Shawn Searles · Austin, US
Faisal A. Syed · Austin, US
Nicholas T. Humphries · Austin, US

Key dates

Filing date	Mar 31, 2008
Grant date	Apr 19, 2011
Priority date	—
Expiry date	Feb 2, 2029

Classification

Technology area (CPC H)Electricity
CPC primaryH03L7/0812
WIPO fieldComputer technology
WIPO sectorElectrical engineering

Abstract

A transceiver (222) includes a receive circuit (320), a transmit circuit (340), a shared delay locked loop (DLL) (360), and a controller (210). The receive circuit (320) has a first input coupled to an external data terminal, a second input coupled to an external data strobe terminal, and an output coupled to an internal data terminal. The transmit circuit (340) has a first input coupled to the internal data terminal, a second input for receiving an internal clock signal, a first output coupled to the external data terminal, and a second output coupled to the external data strobe terminal. The controller (210) enables the shared DLL (360) for use by the receive circuit (320) during a receive cycle, and enables the shared DLL (360) for use by the transmit circuit (340) during a transmit cycle.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.