Memory device with error correction capability and preemptive partial word write operation
US7930615B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | May 31, 2007 |
| Grant date | Apr 19, 2011 |
| Priority date | — |
| Expiry date | Feb 16, 2030 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2029/0411
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory device comprises a memory array and error correction circuitry coupled to the memory array. The memory device is configured to perform a partial word write operation in which an error correction code encode process for the given retrieved word is initiated prior to completion of an error correction code decode process for the given retrieved word based on an assumption that the error correction code decode process will not indicate an error in the given retrieved word. If the error correction code decode process when completed indicates an error in the given retrieved word, the error in the given retrieved word is corrected in the error correction circuitry, and the error correction code encode process is restarted using the corrected word. The error correction code decode process and an associated correct process are thereby removed from a critical timing path of the partial word write operation.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.