Methods for automatically generating fault mitigation strategies for electronic system designs
US7930662B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Nov 4, 2008 |
| Grant date | Apr 19, 2011 |
| Priority date | — |
| Expiry date | Sep 23, 2029 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F30/3323
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Approaches for generating a design of an electronic system are disclosed. In one approach, for each of one or more components of a first specification of the design, an error mitigation technique is selected from among multiple different error mitigation techniques in response to user-specified data associated with the first specification of the design. A second specification of the design is automatically generated from the first specification. The second specification includes error mitigation logic corresponding to each selected error mitigation technique for each of the one or more components. The second specification of the design is stored for subsequent processing.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.