Structure for integrated circuit for measuring set-up and hold times for a latch element
US7930663B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Apr 29, 2008 |
| Grant date | Apr 19, 2011 |
| Priority date | — |
| Expiry date | May 27, 2029 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C11/41
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A design structure for an integrated circuit (IC) includes circuitry for measuring accurately at least one of set-up and hold times of a flip-flop included in the IC design. The circuitry uses data determined at the location of the flip-flop in the IC, and includes a first delay element driven by a first clock and configured to supply a zero-delay value of the first clock to a first flip-flop. The circuitry also includes a second delay element having a selectable delay, the second delay element configured to supply a first delayed version of the first clock to a second flip-flop, wherein an output of the first flip-flop is coupled to an input of the second flip-flop. A third delay element has a selectable delay and is coupled in series with the second delay element to supply a second delayed version of the first clock to a third flip-flop, and an output of the second flip-flop is coupled to an input of the third flip-flop. The second delayed version of the clock signal drives the third flip-flop to monitor the second flip-flop delay, the possible “pass set-up” state, and “pass hold” state outputs are determined for the second flip-flop based on a final test state of the second and …
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.