Method of manufacturing a semiconductor device
US7932149B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | May 19, 2009 |
| Grant date | Apr 26, 2011 |
| Priority date | — |
| Expiry date | Aug 5, 2029 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10B43/40
Abstract
In a method of manufacturing a semiconductor device, a tunnel insulation layer is formed on a substrate. A charge trapping layer is formed on the tunnel insulation layer. A protection layer pattern or a mold is formed on the charge trapping layer. Charge trapping layer patterns are formed on the tunnel insulation layer by etching the charge trapping layer using the protection layer pattern or the mold. The charge trapping layer patterns may be spaced apart from each other. Blocking layers are formed on the charge trapping layer patterns, respectively. A gate electrode is formed on the blocking layers and the tunnel insulation layer using the protection layer pattern or the mold.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.