Method and apparatus for performing electrical rule checks on a circuit design
US7934187B1 · kind B1 · utility
Assignee
Inventor
Key dates
| Filing date | Jun 29, 2006 |
| Grant date | Apr 26, 2011 |
| Priority date | — |
| Expiry date | May 29, 2027 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F30/398
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Method, apparatus, and computer readable medium for performing electrical rule checks (ERCs) on a circuit design are described. In one example, a hierarchy of cell instances is created from a schematic database for the circuit design. The hierarchy is traversed to produce master nets. Each of the master nets is associated with shorted nets in the circuit design. The hierarchy is traversed to produce ERC nets. Each of the ERC nets is associated with effectively shorted nets in the circuit design. At least one pair of the effectively shorted nets is effectively shorted across a transistor. At least one ERC is performed on the circuit design using the master nets and the ERC nets.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.